1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor, a semiconductor, a circuit substrate and an electronic apparatus and, in particular, to a semiconductor chip suitable for three-dimensional packaging and to a method of manufacturing the same.
Priority is claimed on Japanese Patent Applications No. 2003-72337, filed Mar. 17, 2003, and No. 2003-76111, filed Mar. 19, 2003, the content of which is incorporated herein by reference.
2. Description of Related Art
Reductions in size and weight are demanded in portable electronic apparatuses such as mobile telephones, notebook computers, and personal digital assistance (PDA).
Accompanying this, packaging space for semiconductor chips in the aforementioned electronic apparatuses is extremely restricted, and high density semiconductor chip packaging is a problem. Therefore, three-dimensional packaging technology such as that shown in, for example, in Japanese Unexamined Patent Application, First Publication No. 2002-25948 has been devised. Three-dimensional packaging technology is a technology that achieves high density packaging of semiconductor chips by stacking semiconductor chips together, and connecting each semiconductor chip by wiring.
Here, FIG. 20 is a side cross-sectional view of stacked semiconductor chips, FIG. 21 is an enlarged view of the portion A in FIG. 20.
As shown in FIG. 20, a plurality of electrodes 234 are formed in each semiconductor chip 202 used in three-dimensional packaging technology. The electrodes 234 are formed so as to penetrate the semiconductor chip 202 from an electrode pad (not shown) formed in an active surface 210a of the semiconductor chip 202 to a rear surface 210b of the semiconductor chip 202. The portion of the electrode 234 that fills the through hole in the semiconductor chip 202 is called a plug portion, while the portion that protrudes at a front surface of the semiconductor chip 202 is called a post portion. Note that, in order to prevent short-circuits between signal wires and an earth, as shown in FIG. 21, an insulating film 222 is formed at an inner surface of the through hole 232 in the semiconductor chip.
As shown in FIG. 21, a solder layer 240 is formed at a top end surface of the post portion 235 of the electrode 234. The semiconductor chips 202a and 202b are stacked in a position such that the bottom surface of the plug portion 236 of the electrode 234 of the upper semiconductor chip 202a is placed on a top surface of the post portion 235 of the electrode 234 of the lower semiconductor chip 202b. Here, the semiconductor chips 202a and 202b are mutually compressed while the solder layer 240 is melted by reflow. As a result, a solder alloy is formed in the portion of contact between the solder layer 240 and the electrode 234, so that the two are mechanically and electrically bonded. The semiconductor chips 202a and 202b are thus connected by wiring.
However, there is a concern that the solder layer 240 that is melted by reflow will be deformed upwards along the outer circumference of the plug portion 36 of the electrode 234 of the upper semiconductor chip 202a, and will make contact with the rear surface 210b of the upper semiconductor chip 202a. This would cause the problem of short-circuiting occurring between the signal wiring and the ground as the signal wiring is connected to the solder layer 240 while the ground is connected to the rear surface 210b of the semiconductor chip 202a. 
Moreover, the bottom surface of the plug portion 236 of the electrode 234 is exposed to the air in the semiconductor chip 202a before it is stacked. Therefore, if there is a lengthy time between the formation and the stacking of the semiconductor chip 202a, it is possible that the bottom surface of the plug portion 236 of the electrode 234 will become oxidized, and that the wettability thereof will deteriorate. In addition, if the semiconductor chip 202a is stacked with the electrode 234 in an oxidized state, it is difficult for solder alloy to be formed in the bond portion between the solder layer 240 and the electrode 234, thereby creating the problem of conduction failures occurring between electrodes. This results in there being a reduced yield of three-dimensionally packaged semiconductor devices.
The present invention was conceived in order to solve the above described problems and it is an object thereof to provide a method of manufacturing a semiconductor device, a semiconductor device, a circuit substrate, and an electronic apparatus in which short circuiting between signal wiring and a ground is prevented, and in which the problem of conduction failures occurring between electrodes during stacking is prevented.